![Epcs Serial Flash Controller Qsys](https://kumkoniak.com/90.jpg)
![Epcs Serial Flash Controller Qsys Epcs Serial Flash Controller Qsys](https://www.mikrocontroller.net/attachment/340058/QSYS_Rom_Init.png)
The board does have the newer 64Mbit flash chip, and I've included the override file with an entry for. I've tried setting CPU reset & exception vectors to either SDRAM (this allows the processor to run & code to execute, but no flash access), or to EPCS (which results in the Nios Console view in Eclipse not loading, and the program fails to launch). The EPCS reset is connected to both the clk_reset (reset output from clock source) and jtag_debug_module_reset from Nios II the epcs_control_port is connected to both data master and instruction master ports on the Nios II CPU. At this point I'm just trying to make sure I can communicate with the flash using the nios2-flash-programmer (with -epcs and -debug flags).
![Epcs Serial Flash Controller Qsys Epcs Serial Flash Controller Qsys](https://www.fpgakey.com/familyImages/202005/EPCS64%201.png)
(Other system components include the UP Clock Signals for SDRAM Clock, SDRAM Controller, Sys ID, JTAG UART, and Interval Timer). I've set up a Nios II system in Qsys and included the EPCS Serial Flash Controller. I'm having trouble accessing the EPCS Flash on a new DE0 Nano board.
![Epcs Serial Flash Controller Qsys](https://kumkoniak.com/90.jpg)